A latch is typically the first stage of a register element. In a dynamic or a timing-critical application, dual monotonic signal outputs are required. “Monotonic” refers to a data transition characteristic of the output signals of the latch. The output signals are “monotonic” when exactly one of these output signals transitions, and transitions only once, during a given clock phase. A clock-gated dynamic latch has the desired behavior, but has the drawback of using ratioed logic. That is, to allow the latch to be written into, one of the cross-coupled devices is provided a lesser output drive capability, so that the new data can overwrite the existing data by contending with and overcoming the drive strength of this lesser drive capability. In the ratioed logic circuit, a pull-down NMOS device is required to pull a dynamic node to ground reference (i.e., voltage Vss,) over PMOS pull-up devices (“keeper device”) that attempts to drive the dynamic node to the supply voltage (i.e., voltage Vdd). Consequently, ratioed logic circuits require larger pull-down devices. Therefore, greater power and area than desired are required.
Ratioed logic suffers from a number of disadvantages. First, the contention between pull-up PMOS transistors or pull-down NMOS transistors during the write process dissipates power. Second, the contention present when the latch is written into requires time to resolve, hence affecting evaluation time performance, thus slowing circuit operation. Ratioed logic also does not scale well over a large range of operating voltages, and tends to fail more frequently at the lower end of the operating voltages. In addition, ratioed logic circuits are sensitive to variations in process parameter values, and are therefore susceptible to failure modes relating to process variations.